L3 partitioning - Arc protection - Bay control and measurement - Motor protection - Transformer protection - 2 winding - Busbar differential protection (low impedance) - Feeder protection - Voltage regulation - Busbar protection (voltage and frequency) - Capacitor bank protection - Interconnection protection - Power management/Load shedding - Back-up protection - Engineering Manual - SSC600 Smart substation control and protection - SSC600 - 1.5 - IEC - ANSI - 18.12.2024

SSC600 and SSC600 SW Engineering Manual

L3 cache should be partitioned so that virtual CPUs 1 and 2 have a separate 6 MiB or larger last-level cache partition in total.

For checking the L3 cache execute sudo pqos -D on the host, and look for the L3 CAT and L3 Cache sections. They contain the following information

  • Way size - The size of one single cache block
  • Ways contention bit-mask - Bit-mask of cache blocks that are shared with peripherals
  • Num ways - Number of cache blocks

Example output which shows that the L3 can be divided into 20 blocks, each 1310720 bytes (1MB) in size, and the two last blocks are shared with peripherals.

Allocation

Cache Allocation Technology (CAT)

L3 CAT

CDP: unsupported

Non-Contiguous CBM: unsupported

I/O RDT: unsupported

Num COS: 15

Way size: 1310720 bytes

Ways contention bit-mask: 0xc0000

Min CBM bits: 1

Max CBM bits: 20

Cache information

L3 Cache

Num ways: 20

Way size: 1310720 bytes

Num sets: 20480

Line size: 64 bytes

Total size: 26214400 bytes